Conventionally, there are known high-frequency amplifiers such as those described in JP-B Nos. 3125723 and 3514720, JP-A Nos. 2005-228196, H09-130157, 2001-94362, 2001-284984, and 2005-184838.
JP-B No. 3125723 discloses, as a high-frequency amplifier, a bias circuit for an emitter-grounded amplifier circuit wherein a bias circuit for bipolar transistors to amplify signals has a feedback loop configuration, and a resistor for self-bias is removed that was grounded to this bias circuit. According to JP-B No. 3125723, it is possible to make input resistance as viewed from the input terminal substantially large by removing the resistor in the bias circuit.
FIG. 5 of JP-B No. 3514720 discloses a power amplifier wherein a distortion compensation diode is connected via a first resistor between the base and base bias feed terminals of a signal amplifying bipolar transistor 101, and the connection point of the first resistor and the distortion compensation diode is grounded via a temperature compensation diode. According to JP-B No. 3514720, variations of the bias point can be suppressed by this configuration even when temperature changes.
FIG. 1 of JP-A No. 2005-228196 discloses a bias voltage supply circuit having a bias voltage supply point connected to the base of a high-frequency amplifier transistor and a constant voltage source, and wherein a rectifier transistor and a constant current source are connected to the bias voltage supply point. According to JP-A No. 2005-228196, since the bias voltage supply circuit has bias characteristics that the input power increases until its peak and then drops, it is possible to provide a high-frequency amplifier circuit with excellent saturation characteristics.
FIG. 5 of JP-A No. H09-130157 discloses a pre-amplifier (a current-voltage converter) having a feedback loop including a current signal input means, a signal amplifier transistor, and a control current source that is connected to the input means to shunt the current signals. According to JP-A No. H09-130157, this configuration allows an average output potential to be made constant by automatic adjustment of the current distribution ratio when a large amount of current is input.
JP-A No. 2001-94362 discloses a transmission amplifier wherein a transistor with the collector and base thereof connected together is used as a parent-side transistor constituting a current mirror, and a low-pass filter is composed of an out-of-chip inductor connected to the bases of a pair of transistors and a capacitor connected between the base and emitter of the parent-side transistor. According to JP-A No. 2001-94362, this configuration prevents high-frequency signals from being input to the parent-side transistor and thereby prevents a drop in the base bias potential even at a high output, thus making it possible to realize a high-output transmission amplifier.
JP-A No. 2001-284984 discloses a power amplifier module including an amplifier to power-amplify an input signal; a reference amplifier that includes a current mirror circuit and generates the DC component of an input signal corresponding to the input power level; and a DC amplifier (a dummy circuit) to amplify and supply this DC component to the amplifier. According to JP-A No. 2001-284984, it is possible to reproducibly realize a high-efficiency and low-distortion power amplifier module.
JP-A No. 2005-184838 discloses a semiconductor device including a bias generator connected to the gate terminal of a MOS transistor; a low-pass filter circuit connected between the input signal input section and the bias generator; and a high pass filter circuit connected between the input section and the gate terminal of the MOS transistor. The invention disclosed in JP-A No. 2005-184838 is intended to provide a technology to correctly compensate for the variations of bias condition in a MOS device attributable to device temperature variations and/or process variations.
Also, there is known an amplifier having a dual bias feed circuit as described in Eiji Taniguchi et al. “Dual bias feed SiGe HBT linear low-noise amplifier”, IECE Journal MW2001-25, OPE2001-12 (2001-06), pp. 1-5. FIGS. 12 and 14 herein show the circuits disclosed in this document. That is, this document refers to the inductor bias feed circuit 710 and the resistor bias feed circuit 810 shown in FIGS. 12 and 13, and proposes the dual bias feed circuit shown in FIG. 14.
In FIG. 12, 701 to 703 denote transistors, 704 denotes a resistor, and 705 denotes an inductor. In FIG. 13, 801 to 803 denote transistors, 804 denotes a capacitor, 805 to 808 denote resistors, and 830 to 831 denote matching circuits. The dual bias feed circuit in FIG. 14 is a combination of the resistor bias feed circuit 810 and the diode bias feed circuit 910. The diode bias feed circuit 910 includes transistors 901 to 903 and a resistor 904. According to the Taniguchi, linearity of the resistor bias feed circuit is improved by introducing the dual bias feed circuit.